                                     
                             CIRCUIT.TXT File
                                     
                       HP 48 digital logic simulator

From: ard at siva.bristol.ac.uk (Tony Duell)

Date: October 15, 1990


Overview
--------

Here's a digital circuit simulator for the HP 48.  It has 8 internal
primitives: AND, OR, XOR, NOT, BUF (buffer), HI (node tied to logic 1), LO
(node tied to logic 0) and CLK (clock generator of definable high and low
times).  It also supports nested macros defined from these elements.


Definitions
-----------

A circuit is entered as a list of lists.  Each sublist defines one gate (or
macro-circuit) in the design.  The format of the sublist is as follows :

{"NAME" I1 I2 I3..}

Where NAME is either one of the primitives above or the variable name where
the macro is stored entered as a string.  I1, I2, etc. are the names of the
nodes in your circuit, and must be valid HP 48 name objects (or in the case
of "CLK", the first 2 arguments are integers).  For example:

{"AND" A1 A2 Both}

is the representation of the circuit :

  A1----------|\
              | )--------- Both
  A2----------|/

In the primitives, the inputs are always given first, and I suggest you do
the same in macros (see below).


TWO-INPUT GATES

There are 3 types of 2-input gate defined, AND, OR and XOR. The formats
are:

List Format           Equivalent Expression (which you don't enter)
---------------       ---------------------------------------------
{"AND" A1 A2 Q}       Q = A1 AND A2
{"OR" A1 A2 Q}        Q = A1 OR A2
{"XOR" A1 A2 Q}       Q = A1 XOR A2


ONE-INPUT GATES

There are 2 types of 1-input gate, NOT and Buffer:

List Format          Equivalent Expression
--------------       ---------------------
{"NOT" A B}          B = NOT A
{"BUF" A B}          B = A


TIED NODES

A node can also be defined as permanently high or low:

List Format         Equivalent Expression
-------------       ---------------------
{"HI" A}            A = 1
{"LO" A}            A = 0


CLOCK GENERATORS

The high and low times of the clock generator are defined in terms of time-
steps, which are defined as 1 horizontal pixel on the final timing diagram.

Note that all gates have a propagation delay of one time-step. The format
for defining a clock generator is :

{"CLK" hi_time lo_time Output}

Where hi_time and lo_time are real numbers giving the number of time-steps
that the output will be high or low respectively and Output is the node
name for the output.  For example:

{"CLK" 4 4 A}

defines that node A will be low for 4 time-steps, high for 4 time-steps,
low for 4 time-steps, etc.


Installation
------------

Transfer and attach the library object CIRCUIT.LIB as described in the
README file.


Operation
---------

A circuit is defined by creating a list of these sub-lists.  For example:

{{"CLK" 2 2 A} {"CLK" 4 4 B} {"AND" A B C}}

The only commands you need to know to run the simulator are as follows:

COMPILE   Takes the variable name where a circuit is stored in level 1 of
          the stack and sets up the internal variables to represent that
          circuit.  Use this before attempting to simulate.

NODES     Takes a list of nodes that are to appear in the final timing
          diagram in level 1, and stores it in the internal variable OUT.L

ALL       Sets up OUT.L to contain ALL nodes in the circuit (including the
          internal ones in macros).  Only useful for simple circuits.

SIM       Takes a length of simulation in level 1 (a real number, max 100)
          and plots the timing diagram (in PICT) for the given circuit.
          After it has finished, press any key (except ATTN) to exit and
          restore the stack display.

---------------------------------------------------------------------------
Example:

Given the circuit defined above in top of stack, store it in 'CSH', then
execute the following

'CSH' |COMPILE|            set up this circuit
|ALL|                      we'll show all nodes
100 |SIM|                  draw a timing diagram.
---------------------------------------------------------------------------


OTHER VARIABLES

DEMO      An example cirucit definition using a full-adder.

FADD      A full-adder definition based on HADD.

HADD      A half-adder defintion.

MUX       A two-input multiplexer definition.

MUX4      A four-input multiplexer based on MUX.


MACROS

A macro-circuit is a bit like a subroutine--it's a part of a circuit (e.g.
a half-adder or a flip-flop) that is used several times.  For an example,
see the variable HADD in the directory which contains the macro that
defines a half adder.  Each macro definition has the form:

{{External list} {{GATE1}{GATE2}...}}

where {{GATE1}{GATE2}...} is the circuit description of the macro as
defined above, and {External list} is the list of external connections.
For example, the 2-input multiplexer (variable MUX) in the directory
CIRCUIT:

           |\
SEL --+----| >o------------|\
      |    |/              | )--|
      |             A------|/   ------\----\
      |                                )    )-------- Y
      |             B------|\   ------/----/
      |                    | )--|
      +--------------------|/

Now, the external connections are SEL, A, B and Y

           |\     NS
SEL --+----| >o------------|\
      |    |/              | )--| YA
      |             A------|/   ------\----\
      |                                )    )-------- Y
      |             B------|\   ------/----/
      |                    | )--| YB
      +--------------------|/

I've now labeled the internal nodes (NS, YA, YB)

Thus, we get the definition:

{{SEL A B Y}{{"NOT" SEL NS} {"AND" A NS YA} {"AND" B SEL YB} {"OR" YA YB
Y}}}

If this is stored in the variable MUX , the element {"MUX" X Y Z GO} will
be valid, with the correspondence:

X  ->  SEL
Y  ->  A
Z  ->  B
GO ->  Y

Circuits (and other macros) can be defined in terms of MUX.


EXAMPLE: THE FULL ADDER

I have included a simple example of the single-bit full adder to
demonstrate the features of this logic simulator.  In the variable HADD is
the macro for a half-adder, whereas in FADD, I have given the macro for a
full-adder, defined in terms of HADD.  In the variable DEMO, I have defined
a simple circuit with one full-adder, with its 3 input driven from clock-
generators in the ratio 1:2:4. Here's how to run the demonstration:

'DEMO' |COMPILE|              Define the circuit.
{M N P S C} |NODES|           Only display the inputs and outputs.
100 |SIM|                     Display the timing diagram (after it's
                              finished, press any key to exit).

I am quite willing to answer questions about how this program works, but as
it's likely to be quite long, I'll only post it to the net if there is
sufficient interest.

-Tony Duell
ARD @ UK.AC.BRIS.PVA  (JANET)
ARD @ SIVA.BRIS.AC.UK (BITNET)

(This program and its documentation are public domain. They may be freely
copied, used and published in user-group newsletters provided that my name
remains attached to them. They may not be sold for profit.)

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V 1.0 04/27/92 12:13 PM
